Slide1:
Intro. This lecture covers test processes and equipment.
Slide2:
Automatic Test Pattern Generation(ATPG): EDA method used to determine an input test sequence that, when applied to a digital ckt., enables testers to distinguish between correct circuit behavior and faulty circuit behavior caused by defects.
Diagnostic Testing: Trying to determine as to why the wafer yield is low etc…testing aimed particularly at determining cause of chip failure, so that corrective action can be taken
Design for Testability: Adding extra logic blogs in the design, so that later testing becomes easier.
Scan design: Registers (FF or latches) are connected in one or more scan chains which are used to gain access to internal nodes in the chip. Test patterns are shifted in via the scan-chains, clock signals are pulsed to test the circuit and then results are shifted out to chip output chains and compared against expected “good-machine” results.
Debug using DFT features:
- Use scan chains
- Chip is used in normal functional mode
- At any point, stop chip clock and reconfigure it into test mode
- Either dump full internal state into scan chain, or set state using scan chain
Uses of Debug DFT:
- Initialize memory elements.
- Bring system to known state without going through many clock cycles.
