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	<title>A new dimension &#187; VLSI Verification</title>
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		<title>A new dimension &#187; VLSI Verification</title>
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		<item>
		<title>Lec3</title>
		<link>http://atchuth.wordpress.com/2008/02/22/lec3/</link>
		<comments>http://atchuth.wordpress.com/2008/02/22/lec3/#comments</comments>
		<pubDate>Sat, 23 Feb 2008 04:00:45 +0000</pubDate>
		<dc:creator>atchuth</dc:creator>
				<category><![CDATA[VLSI Verification]]></category>

		<guid isPermaLink="false">http://atchuth.wordpress.com/?p=33</guid>
		<description><![CDATA[Main points to take away:
Fault models, Concepts of fault equivalence, fault collapsing and fault dominance.
Number of fault sites in a boolean gate circuit =#PI + #gates + #(fanout branches)
Primary inputs and fanout branches are checkpoints
Check point theorem: A test that detects all single(multiple)  stuck-at faults on all checkpoints of a combinational circuit, also detects all [...]<img alt="" border="0" src="http://stats.wordpress.com/b.gif?host=atchuth.wordpress.com&blog=1432244&post=33&subd=atchuth&ref=&feed=1" />]]></description>
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		<title>Lec 2, Slide 6 through 20.</title>
		<link>http://atchuth.wordpress.com/2008/02/22/lec-2-slide-67/</link>
		<comments>http://atchuth.wordpress.com/2008/02/22/lec-2-slide-67/#comments</comments>
		<pubDate>Fri, 22 Feb 2008 23:06:28 +0000</pubDate>
		<dc:creator>atchuth</dc:creator>
				<category><![CDATA[VLSI Verification]]></category>

		<guid isPermaLink="false">http://atchuth.wordpress.com/?p=32</guid>
		<description><![CDATA[Characterization test: Used to rank test vectors using score-boarding. 
Scoreboarding is a centralized method, used in the CDC 6600, for dynamically scheduling a pipeline so that the instructions can execute out of order when there are no conflicts and the hardware is available.
NAC Diode (Net Area check diode): it is a diode, a PN-junction connected [...]<img alt="" border="0" src="http://stats.wordpress.com/b.gif?host=atchuth.wordpress.com&blog=1432244&post=32&subd=atchuth&ref=&feed=1" />]]></description>
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		<title>Lec 2, Slides 4 and 5</title>
		<link>http://atchuth.wordpress.com/2008/02/22/lec-2-slides-4-and-5/</link>
		<comments>http://atchuth.wordpress.com/2008/02/22/lec-2-slides-4-and-5/#comments</comments>
		<pubDate>Fri, 22 Feb 2008 22:35:01 +0000</pubDate>
		<dc:creator>atchuth</dc:creator>
				<category><![CDATA[VLSI Verification]]></category>

		<guid isPermaLink="false">http://atchuth.wordpress.com/?p=31</guid>
		<description><![CDATA[Verification testing includes circuit verification and power verification.
Circuit verification: Current, setup time, hold time, clock skew etc , memory check.
Power verification: Avg, max, drop(see inductance),

VRM: Voltage Regulator Module
A voltage regulator module (VRM) is an installable module that senses a computer&#8217;s microprocessor voltage requirements and ensures that the correct voltage is maintained. If you are changing [...]<img alt="" border="0" src="http://stats.wordpress.com/b.gif?host=atchuth.wordpress.com&blog=1432244&post=31&subd=atchuth&ref=&feed=1" />]]></description>
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		<title>Lec 2, Sl 3</title>
		<link>http://atchuth.wordpress.com/2008/02/22/lec-2-sl-3/</link>
		<comments>http://atchuth.wordpress.com/2008/02/22/lec-2-sl-3/#comments</comments>
		<pubDate>Fri, 22 Feb 2008 22:24:51 +0000</pubDate>
		<dc:creator>atchuth</dc:creator>
				<category><![CDATA[VLSI Verification]]></category>

		<guid isPermaLink="false">http://atchuth.wordpress.com/?p=30</guid>
		<description><![CDATA[The main point here to note is that verification is being done at 2 stages 1) during/end of design  and after fab (where it is called design validation)
Logic Verification: Using software simulation/emulation
Design Validation: Verification using testers.
       <img alt="" border="0" src="http://stats.wordpress.com/b.gif?host=atchuth.wordpress.com&blog=1432244&post=30&subd=atchuth&ref=&feed=1" />]]></description>
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		<title>Lecture 2, Slide 2</title>
		<link>http://atchuth.wordpress.com/2008/02/22/lecture-2-slide-2/</link>
		<comments>http://atchuth.wordpress.com/2008/02/22/lecture-2-slide-2/#comments</comments>
		<pubDate>Fri, 22 Feb 2008 22:17:48 +0000</pubDate>
		<dc:creator>atchuth</dc:creator>
				<category><![CDATA[VLSI Verification]]></category>

		<guid isPermaLink="false">http://atchuth.wordpress.com/?p=29</guid>
		<description><![CDATA[Slide1: 
Intro. This lecture covers test processes and equipment.
Slide2:
Automatic Test Pattern Generation(ATPG):  EDA method used to determine an input test sequence that, when applied to a digital ckt., enables testers to distinguish between correct circuit behavior and faulty circuit behavior caused by defects.
Diagnostic Testing: Trying to determine as to why the wafer yield is low etc&#8230;testing [...]<img alt="" border="0" src="http://stats.wordpress.com/b.gif?host=atchuth.wordpress.com&blog=1432244&post=29&subd=atchuth&ref=&feed=1" />]]></description>
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